1. Field of the Invention
The present invention relates to a piezo electric transformer driving circuit and a cold cathode tube illuminating device using the same, and, more specifically, relates to a piezo electric transformer driving circuit in a driving circuit of a cold cathode tube used as a back light for a liquid crystal displaydevice which, when obtaining an electric power of a high step-up voltage necessary for driving the cold cathode tube through driving a piezo electric transformer, permits the high voltage step-up through driving the piezo electric transformer without necessitating a transistor having a high dielectric break down voltage and hardly breaks the driving transistor.
2. Background Art
Conventionally, a cold cathode tube has been generally used as a back light disposed at the back side of a liquid crystal member in a liquid crystal display device. A light-on voltage of a cold cathode tube is high, for example, more than 1000 V and such a high voltage is obtained by stepping up a voltage of about 5.about.6 V. For this purpose a lighting-on circuit therefor uses an inverter circuit, and because of circuit size reduction demand in these days an inverter circuit making use of a piezo electric transformer is currently being used instead of an electro magnetic type inverter circuit.
FIG. 3 is such a cold cathode tube illuminating device making use of a piezo electric transformer.
Numeral 10 generally designates the cold cathode tube illuminating device and numeral 1 is a control circuit therefor, 5 is a piezo electric transformer driving circuit therefor, 6 is a piezo electric transformer and 7 is a cold cathode tube, in that a cold cathode fluorecent lamp. The control circuit 1 is constituted by a pulse oscillation circuit 2, a flip-flop circuit (FF) 3 and buffer amplifier 4a and 4b which receive outputs from the flip-flop circuit 3. A Q output and an inverted side output (Q output, hereinbelow called as Q bar output) generated with the Q output of the flip-flop circuit (FF) 3 are respectively applied via the buffer amplifiers 4a and 4b to the piezo electric transformer driving circuit 5. Further, the control circuit 1 is provided with a drive halting circuit 8. When a manipulation switch SW such as a power source switch, a switch for halting the driving circuit or a light-off switch for a liquid crystal back light is shifted from ON to OFF, the drive halting circuit 8 generates a light halting signal S (or a light-off signal S) for halting lighting of the cold cathode tube 7 in response to the OFF signal and applies the signal to the flip-flop circuit 3 to halt the operation thereof.
In the above example, the primary side of the piezo electric transformer 6 is driven via two circuit line systems which are driven alternatively and provides a doubled driving signal to the primary side thereof to thereby produce a high voltage sinusoidal or the like signal at the secondary side thereof. In this instance a driving voltage frequency from several tens kHz to several handreds kHz is used for the piezo electric transformer 6.
The piezo electric transformer driving circuit 5 is constituted by a first switching circuit 51 and a second switching circuit 52 both are provided between a power source line V.sub.DD and a grounding line GND. The first switching circuit 51 is constituted by a series circuit including a coil L1 provided at the side of the power source V.sub.DD and an N channel MOSFET transistor Q1 of which drain side is connected to the coil L1 and of which source side is grounded. An output P1 of the transistor Q1 appears at the juncture between the drain of the transistor Q1 and the coil L1 and is connected to a primary side electrode 61 of the piezo electric transformer 6. The gate of the transistor Q1 is connected to receive the Q bar output Pc of the flip-flop circuit 3 via the buffer ampifier 4a.
The second switching circuit 52 is constituted by another series circuit including a coil L2 provided at the side of the power source V.sub.DD and an N channel MOSFET transistor Q2 of which drain side is connected to the coil L2 and of which source side is grounded. An output P2 of the transistor Q2 appears at the juncture between the drain of the transistor Q2 and the coil L2 and is connected to a primary side electrode 62 of the piezo electric transformer 6. The gate of the transistor Q2 is connected to receive the Q output Pb of the flip-flop circuit 3 via the buffer amplifier 4b.
In the above explained circuit the coils L1 and L2 are inserted in series with the piezo electric transformer 6. The reason of employing such circuit structure is to efficiently utilize a voltage oscillation by the piezo electric transformer 6 determined depending on the capacitive component of the piezo electric transformer 6 and the inductance component of the coils. Accordingly, the inductance values of the coils L1 and L2 are respectively selected in view of the capacitive component of the piezo electric transformer 6 so as to resonate with the frequency of the driving signal, thereby the conversion efficiency of the circuit is increased.
The cold cathode tube 7 is connected through one electrode thereof to a secondary side electrode 63 of the piezo electric transformer 6 and the other electrode thereof is connected to the ground GND via a parallel circuit of a resistor R and a diode D.
Further, the control circuit 1 includes a further control circuit which detects the voltage of the resistor R and operates to keep the oscillation frequency of the pulse oscillation circuit 2 at a constant frequency, however, such further control circuit does not relates directly to the present invention, therefore the illustration and explanation thereof is omitted.
The driving and halting operation of the above explained circuit is explained with reference to waveform diagrams illustrated in FIGS. 4(a)-4(f). At first, the flip-flop circuit 3 receives a pulse signal Pa as illustrated in FIG. 4(a) from the pulse oscillation circuit 2 and outputs as the Q output the pulse signal Pb as illustrated in FIG. 4(b) which is formed by dividing the pulse signal Pa by 1/2. At the same time the flip-flop circuit 3 also generates the pulse signal Pc as illustrated in FIG. 4(c) which is an inversion of the Q output as a Q bar output. In response to the respective outputs the respective transistors Q1 and Q2 are turned ON and generate respective signals as illustrated in FIGS. 4(e) and 4(f) as the outputs P1 and P2 and apply the same to the primary sides of the piezo electric transformer 6. As a result, a high voltage sinusoidal or the like signal is obtained at the secondary side of the piezo electric transformer 6.
When halting lighting of the cold cathode tube 7 under the above explained driving condition, the output of the flip-flop circuit 3 is halted which is located at a pre-stage of the piezo electric transformer driving circuit 5. For example, when a light halting signal S is generated from the drive halting circuit 8 at a time point t1 as illustrated in FIG. 4(d) and the output of the flip-flop circuit 3 is halted, high voltage fly back pulses F1 and F2 are generated at the outputs P1 and P2 of the transistors Q1 and Q2, because any discharge routes of energy accumulated in the coils L1 and L2 are lost.
In the above explained piezo electric transformer driving circuit 5, for the transistors Q1 and Q2 performing the switching operation transistors having a higher electric break down voltage than that of the fly back pulses F1 and F2 are used so as to withstand the fly back pulse voltage. For this reason, the transistors to be employed have to have a very high withstand. Moreover, since these transistors suffer from such a high voltage fly back pulses F1 and F2, the transistors are still endangered to be broken down.